Pin Description

Num Name BGA Type Description
1 +5V PWR 5V Power supply
2 +5V PWR 5V Power supply
3 +5V PWR 5V Power supply
4 +5V PWR 5V Power supply
5 GND GND Power Ground
6 GND GND Power Ground
7 GND GND Power Ground
8 GND GND Power Ground
9 NC
10 VRTC PWR RTC Battery, 1.8V
11 NC
12 VDD_3V3B PWR 3.3V Power output, Use for outside IO level
13 NC
14 NC
15 LCD_DATA0 R1 I/O LCD Data line 0[1]
16 LCD_DATA1 R2 I/O LCD Data line 1[1]
17 LCD_DATA2 R3 I/O LCD Data line 2[1]
18 LCD_DATA3 R4 I/O LCD Data line 3 / boot config[1]
19 LCD_DATA4 T1 I/O LCD Data line 4[1]
20 LCD_DATA5 T2 I/O LCD Data line 5[1]
21 LCD_DATA6 T3 I/O LCD Data line 6[1]
22 LCD_DATA7 T4 I/O LCD Data line 7[1]
23 NC
24 NC
25 LCD_DATA8 U1 I/O LCD Data line 8[1]
26 LCD_DATA9 U2 I/O LCD Data line 9[1]
27 LCD_DATA10 U3 I/O LCD Data line 10[1]
28 LCD_DATA11 U4 I/O LCD Data line 11[1]
29 LCD_DATA12 V2 I/O LCD Data line 12[1]
30 LCD_DATA13 V3 I/O LCD Data line 13[1]
31 LCD_DATA14 V4 I/O LCD Data line 14[1]
32 LCD_DATA15 T5 I/O LCD Data line 15[1]
33 NC
34 NC
35 LCDPCLK V5 O LCD peix clock
36 LCDVSYNC U5 O LCD vertical Synchronization signal
37 LCDDE R6 O LCD Data Enable
38 LCDVHYNC R5 O LCD horizontal Synchronization signal
39 NC
40 NC
41 NC
42 NC
43 MMC2_CLK V12 O MMC2 Clock
44 MMC2_CMD T13 O MMC2 Command line
45 MMC2_DAT0 T12 I/O MMC2 Data0
46 MMC2_DAT1 R12 I/O MMC2 Data1
47 MMC2_DAT2 V13 I/O MMC2 Data2
48 MMC2_DAT3 U13 I/O MMC2 Data3
49 USER_BUTTON1 U10 O User KEY 1
50 USER_BUTTON2 T10 O User KEY 2
51 GPIO0_26 T11 O GPIO0_26, Use for RST of SPI to IO
52 GPIO0_27 U12 O GPIO0_27, Use for IRQ of SPI to IO
53 NC
54 NC
55 MMC1_DAT0 U7 I/O EMMC/NAND Data0 (Used by nand on CoreBoard)
56 MMC1_DAT1 V7 I/O EMMC/NAND Data1 (Used by nand on CoreBoard)
57 MMC1_DAT2 R8 I/O EMMC/NAND Data2 (Used by nand on CoreBoard)
58 MMC1_DAT3 T8 I/O EMMC/NAND Data3 (Used by nand on CoreBoard)
59 MMC1_DAT4 U8 I/O EMMC/NAND Data4 (Used by nand on CoreBoard)
60 MMC1_DAT5 V8 I/O EMMC/NAND Data5 (Used by nand on CoreBoard)
61 MMC1_DAT6 R9 I/O EMMC/NAND Data6 (Used by nand on CoreBoard)
62 MMC1_DAT7 T9 I/O EMMC/NAND Data7 (Used by nand on CoreBoard)
63 NC
64 NC
65 GMII2_TXEN R13 O GMII2 Transmit Enable
66 GMII2_RXDV V14 O GMII2 Receive Data Valid
67 GMII2_TXD3 U14 O GMII2 Transmit Data bit 3
68 GMII2_TXD2 T14 O GMII2 Transmit Data bit 2
69 GMII2_TXD1 R14 O GMII2 Transmit Data bit 1
70 GMII2_TXD0 V15 O GMII2 Transmit Data bit 0
71 NC
72 NC
73 GMII2_TXCLK U15 I GMII2 Transmit Clock
74 GMII2_RXCLK T15 I GMII2 Receive Clock
75 GMII2_RXD3 V16 I GMII2 Receive Data bit 3
76 GMII2_RXD2 U16 I GMII2 Receive Data bit 2
77 GMII2_RXD1 T16 I GMII2 Receive Data bit 1
78 GMII2_RXD0 V17 I GMII2 Receive Data bit 0
79 MDIO_CLK M18 O MDIO Clk
80 MDIO_DATA M17 I/O MDIO Data
81 NC
82 NC
83 USB1_DP R17 DIFF USB1 Data plus
84 USB0_DRVVBUS F16 O USB0 Active high VBUS control output
85 USB1_DM R18 DIFF USB1 Data minus
86 USB0_VBUS P15 A USB0 VBUS detection input
87 NC
88 USB0_ID P16 A USB0 OTG ID (Micro-A or Micro-B Plug)
89 USB0_DP N17 DIFF USB0 Data plus
90 USB0_CE M15 A no connect
91 USB0_DM N18 DIFF USB0 Data minus
92 USB1_DRV F15 O USB1 Active high VBUS control output
93 NC
94 USB1_VBUS T18 A USB1 VBUS detection input
95 GPMC_WAIT0
96 USB1_ID P17 A USB0 ID
97 GPMC_OEn_REn T7 O Output Enable (active low). Also used as Read Enable (active low) for NAND protocol memories[2]
98 GPMC_BE0n_CLE T6 O Lower Byte Enable (active low). Also used as Command Latch Enable for NAND protocol memories[2]
99 GPMC_ADVn_ALE R7 O Address Valid or Address Latch Enable depending if NOR or NAND protocol memories are selected. [2]
100 GPMC_WEn U6 O Write Enable (active low) [2]
101 NC
102 NC
103 MMC0_CLK G17 O MMC0 clock
104 MMC0_DAT0 G16 I/O MMC0 data 0
105 MMC0_CMD G18 O MMC0 command
106 MMC0_DAT1 G15 I/O MMC0 data 1
107 MCASP0_AHCLKX A14 O McASP/I2S MCLK
108 MMC0_DAT2 F18 I/O MMC0 data 2
109 NC
110 MMC0_DAT3 F17 I/O MMC0 data 3
111 NC
112 NC
113 NC
114 UART1_CTS D18 O UART5 Clear To Send
115 NC
116 UART1_RTS D17 O UART5 Require To Send
117 UART0_TX E16 O Dbg Uart TX
118 UART1_TX D15 O Uart 1 TX
119 UART0_RX E15 I Dbg Uart RX
120 UART1_RX D16 I Uart 1 RX
121 NC
122 NC
123 UART2_TX /UART5_RTS J15 O Uart 2 Transmit, use for RS485/ UART5 Require To Send
124 UART3_TX C18 O Uart 3 Transmit
125 UART2_RX / UART5_CTS H17 I Uart 2 Receive, use for RS485/UART5 Clear To Send
126 UART3_RX C15 I Uart 3 Receive
127 NC
128 NC
129 UART4_TX E17 O Uart 4 TX/ DCAN1 Receive
130 UART5_TX H18 I Uart 5 Transmit
131 UART4_RX E18 I Uart 4 RX/ DCAN1 Transmit
132 UART5_RX H16 I Uart 5 Receive
133 NC
134 NC
135 I2C0_SCL C16 O I2C0 clock (open drain with pull-up resistor on the SOM)
136 NC
137 I2C0_SDA C17 I/O I2C0 data (open drain with pull-up resistor on the SOM)
138 LEDA I WLED driver，no connect
139 SPI0_CS0 A16 O SPI0 Chip Select
140 SPI0_SCLK A17 O SPI0 Clock
141 SPI0_D1 B16 I/O SPI0 Data 1
142 SPI0_D0 B17 O SPI0 Data 0
143 NC
144 NC
145 MCASP0_ACLKX A13 O McASP0/ I2S Transmit Bit Clock
146 MCASP0_AHCLKR C12 I/O McASP0 Receive Master Clock
147 MCASP0_FSX B13 O McASP0 Transmit Frame Sync
148 GPIO3_16 D12 O gpio3_16 use for Touchscreen reset
149 NC
150 NC
151 NC
152 USER_LED1 B12 O SOM LED, gpio3_18
153 NC
154 MMC0_CD C13 I gpio MMC0 detection, gpio3_19
155 PWR_BUT I PMIC bottom input
156 MCASP0_AXR1 D13 I/O McASP0 Serial Data (IN/OUT)
157 SYS_RESETN Active low Power on Reset
158 EVENT_INTR0 A15 O LCD Enable
159 EXTINTn B18 I External Interrupt to ARM Cortext A8 core
160 EVENT_INTR1 D14 I NET1 INIT
161 NC
162 NC
163 VDD_ADC PWR Supply voltage range for ADC (Connected to 1.8V on CoreBoard)
164 GNDA_ADC GND Analog Ground[3]
165 AIN0 B6 A Analog Input/Output 0, used with touchscreen
166 AIN1 C7 A Analog Input/Output 1, used with touchscreen
167 AIN2 B7 A Analog Input/Output 2, used with touchscreen
168 AIN3 A7 A Analog Input/Output 3, used with touchscreen
169 AIN4 C8 A Analog Input/Output 4, used with touchscreen
170 AIN5 B8 A Analog Input/Output 5
171 AIN6 A8 A Analog Input/Output 6
172 AIN7 C9 A Analog Input/Output 7
173 GNDA_ADC GND Analog Ground[3]
174 GNDA_ADC GND Analog Ground[3]
175 NC
176 NC
177 RGMII1_TRP0 DIFF Ethernet Data 0 Positive
178 JTAG_TRSTn B10 O JTAG TEST RESET (ACTIVE LOW)
179 RGMII1_TRN0 DIFF Ethernet Data 0 Negative
180 JTAG_TDI B11 I JTAG TEST DATA INPUT
181 RGMII1_TRP1 DIFF Ethernet Data 1 Positive
182 JTAG_TCK A12 I JTAG TEST CLOCK
183 RGMII1_TRN1 DIFF Ethernet Data 1 Negative
184 JTAG_TMS C11 O JTAG TEST MODE SELECT
185 NC
186 JTAG_TDO A11 O JTAG TEST DATA OUTPUT
187 RGMII1_TRP2 DIFF Ethernet Data 2 Positive
188 JTAG_EMU0 C14 I/O JTAG Emulation Pin 0 (Used as WP singnal of eeprom on Core Board)
189 RGMII1_TRN2 DIFF Ethernet Data 2 Negative
190 JTAG_EMU1 B14 I/O JTAG Emulation Pin 1 (Used as WDT signal on Core Board)
191 RGMII1_TRP3 DIFF Ethernet Data 3 Positive
192 LEDK1 I WLED driver，no connect
193 RGMII1_TRN3 DIFF Ethernet Data 3 Negative
194 LEDK2 I WLED driver，no connect
195 NC
196 NC
197 RGMII1_ACT O PHY Status LED
198 RGMII1_LED_1000n O PHY 1000M Link LED
199 RGMII1_LED_100n O PHY 100M Link LED
200 NC

Table 3-1

  • LCD_DATA0~LCD_DATA15 as booting selection while power-up, these pins also configured as LCD data-signal in linux kernel, there is a 10K resistance pull-down ground respectively in LCD_DATA0, LCD_DATA1, LCD_DATA3, LCD_DATA5, LCD_DATA8, LCD_DATA10, LCD_DATA11, LCD_DATA12, LCD_DATA13, LCD_DATA15, and a pull-up 3.3V resistance respectively in LCD_DATA2, LCD_DATA4, LCD_DATA6, LCD_DATA7, LCD_DATA9, LCD_DATA14. Please refer to [Figure 4-7 SYS_BOOT config sch]. And please pay attention to the power-up edge status of LCD_DATA0~LCD_DATA15 while designing main board, the CPU selects the booting media according this status, please refer to the chapter 26.15 Booting of 335x_Complete.pdf for more details.
  • Used as nand control-signal on core board
  • Connected to ground on core board